As the drive for faster miniaturized semiconductor devices proceeds apace, it becomes increasingly more difficult to fabricate device features without engendering disadvantages. It is particularly challenging to form gate electrodes having a reduced height and a reduced width, such as a height less than 1,000 Å and a width less than 500 Å, without creating various issues. For example, it is extremely difficult to pattern a gate electrode having a width less than 500 Å by conventional photolithographic techniques with any degree of precision and reproducibility. Moreover, as the gate width decreases, the aspect ratio of the gate electrode disadvantageously increases. However, the gate electrode must be sufficient high to prevent impurity ion penetration therethrough into the underlying gate dielectric layer with an attendant decrease in reliability, as during ion implantation to form deep source/drain regions. Moreover, a high gate height contributes to fringing capacitance between the gate electrode and associated source/drain regions.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor devices comprising transistors having a gate electrode with a reduced width and also a reduced height. There exists a particular need for methodology enabling the fabrication of semiconductor devices comprising transistors with a gate electrode having a width less than 500 Å and a height less than 1,000 Å.